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october 2006 hys72t256000er?3.7?b hys72t256000er?5?b 240-pin registered ddr2 sdram modules ddr2 sdram rdimm sdram rohs compliant internet data sheet rev. 1.0
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys72t256000er-[3.7/5]-b registerd ddr2 sdram module qag_techdoc_rev400 / 3.2 qag / 2006-08-07 2 10202006-ehwj-ot02 hys72t256000er?3.7?b , hys72t256000er?5?b revision history: 2006-10, rev. 1.0 page subjects (major chan ges since last revision) all adapted internet edition all final document
internet data sheet rev. 1.0, 2006-10 3 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 1overview this chapter gives an overview of the 240-pin registered ddr2 sdram modules product family and describes its main characteristics. 1.1 features ? 240-pin pc2?4200 and pc2?3200 ddr2 sdram memory modules. ? 256m 72 module organization and 256m 4 chip organization ? standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply ? 2 gb built with 1gbit ddr2 sdrams in p-tfbga-68-6 chipsize packages ? all speed grades faster than ddr2?400 comply with ddr2?400 timing specifications. ? programmable cas latencies (3, 4 and 5), burst length (8 & 4) and burst type ? auto refresh (cbr) and self refresh ? average refresh period 7.8 s at a t case lower than 85 c, 3.9 s between 85 c and 95 c. ? programmable self refres h rate via emrs2 setting ? programmable partial array refresh via emrs2 settings ? dcc enabling via emrs2 setting ? all inputs and outputs sstl_1.8 compatible ? off-chip driver impedance adjustment (ocd) and on-die termination (odt) ? serial presence detect with e 2 prom ? rdimm dimensions (nominal): 30 mm high and 133.35 mm wide ? based on standard reference layouts raw card ?h? ? rohs compliant products 1) table 1 performance table 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type speed code ?3.7 ?5 unit speed grade pc2?4200 4?4?4 pc2?3200 3?3?3 ? max. clock frequency @cl5 f ck5 266 200 mhz @cl4 f ck4 266 200 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 15 15 ns min. row precharge time t rp 15 15 ns min. row active time t ras 45 45 ns min. row cycle time t rc 60 60 ns
internet data sheet rev. 1.0, 2006-10 4 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 1.2 description the qimonda hys72t256000er-[3.7/5]-b module family are registered dimm modules ?rdimms? with 30 mm height based on ddr2 technology. dimms are available ecc modules in 256m u 72 (2 gb) organization and density, intended for mounting into 240-pin connector sockets. the memory array is designed with 1-gbit double-data-rate- two (ddr2) synchronous drams. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. decoupling capacitors are mounted on the pcb board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and are wr ite protected; the second 128 bytes are available to the customer. table 2 ordering information for rohs compliant products table 3 address format table 4 components on modules product type 1) 1) all product type numbers end with a plac e code, designating the sili con die revision. example: hys72t256000er?3.7?b, indicati ng rev. ?b? dies are used for ddr2 sdram components. for all qimonda ddr2 module and component nomenclature see chapter 6 of this data sheet. compliance code 2) 2) the compliance code is printed on the module label and describes the speed grade, for example ?pc2?4200r?444?12?h0?, where 4200r means unbuffered dimm modules with 4.26 gb/sec module b andwidth and ?444-12? means column address strobe (cas) latency = 4, row column delay (rcd) latency = 4 and row precharge (rp) latency = 4 using the latest jedec spd revision 1.2 and produced on the raw card ?h?. description sdram technology pc2?4200 hys72t256000er?3.7?b 2 gb 1r u 4 pc2?4200r?444?12?h0 1 ranks, ecc 1 gbit ( u 4) pc2?3200 hys72t256000er?5?b 2 gb 1r u 4 pc2?3200r?333?12?h0 1 ranks, ecc 1 gbit ( u 4) dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/column bits raw card 2 gbyte 256m u 72 1 ecc 18 14/3/11 h product type 1) 1) green product dram components 1) dram density dram organisation note 2) 2) for a detailed description of all functionalities of the dram components on these modules see the component data sheet. hys72t256000er hyb18t1g400bf 1 gbit 256m u 4
internet data sheet rev. 1.0, 2006-10 5 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 2 chip configuration this chapter contains the ball configuration. 2.1 chip configuration the ball configuration of t he registered ddr2 sdram dimm is listed by function in table 5 (240 balls). the abbreviations used in columns ball and buffer type are explained in table 6 and table 7 respectively. the ball numbering is depicted in figure 1 . table 5 ball configuration of rdimm ball no. name pin type buffer type function clock signals 185 ck0 i sstl clock signal ck0, comple mentary clock signal ck0 186 ck0 isstl 52 cke0 i sstl clock enables 1:0 note: 2-ranks module 171 cke1 i sstl nc nc ? not connected note: 1-rank module control signals 193 s0 isstl chip select rank 1:0 note: 2-ranks module 76 s1 isstl nc nc ? not connected note: 1-rank module 192 ras isstl row address strobe (ras), column address strobe (cas), write enable (we) 74 cas isstl 73 we isstl 18 reset icmos register reset address signals 71 ba0 i sstl bank address bus 1:0 190 ba1 i sstl 54 ba2 i sstl bank address bus 2 greater than 512mb ddr2 sdrams nc i sstl not connected less than 1gb ddr2 sdrams
internet data sheet rev. 1.0, 2006-10 6 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 188 a0 i sstl address bus 12:0, address signal 10/autoprecharge 183 a1 i sstl 63 a2 i sstl 182 a3 i sstl 61 a4 i sstl 60 a5 i sstl 180 a6 i sstl 58 a7 i sstl 179 a8 i sstl 177 a9 i sstl 70 a10 i sstl ap i sstl 57 a11 i sstl 176 a12 i sstl 196 a13 i sstl address signal 13 nc nc ? not connected note: non ca parity modules based on 256 mbit component 174 a14 i sstl address signal 14 note: ca parity module nc nc ? not connected note: non ca parity module. less than 1 gbit per dram die. 173 a15 i sstl address signal 14 note: ca parity module nc nc ? not connected note: non ca parity module. less than 1 gbit per dram die. ball no. name pin type buffer type function
internet data sheet rev. 1.0, 2006-10 7 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module data signals 3 dq0 i/o sstl data bus 63:0 data input/output balls 4 dq1 i/o sstl 9 dq2 i/o sstl 10 dq3 i/o sstl 122 dq4 i/o sstl 123 dq5 i/o sstl 128 dq6 i/o sstl 129 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 21 dq10 i/o sstl 22 dq11 i/o sstl 131 dq12 i/o sstl 132 dq13 i/o sstl 140 dq14 i/o sstl 141 dq15 i/o sstl 24 dq16 i/o sstl 25 dq17 i/o sstl 30 dq18 i/o sstl 31 dq19 i/o sstl 143 dq20 i/o sstl 144 dq21 i/o sstl 149 dq22 i/o sstl 150 dq23 i/o sstl 33 dq24 i/o sstl 34 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 152 dq28 i/o sstl 153 dq29 i/o sstl 158 dq30 i/o sstl 159 dq31 i/o sstl 80 dq32 i/o sstl 81 dq33 i/o sstl 86 dq34 i/o sstl 87 dq35 i/o sstl 199 dq36 i/o sstl 200 dq37 i/o sstl 205 dq38 i/o sstl ball no. name pin type buffer type function
internet data sheet rev. 1.0, 2006-10 8 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 206 dq39 i/o sstl data bus 63:0 89 dq40 i/o sstl 90 dq41 i/o sstl 95 dq42 i/o sstl 96 dq43 i/o sstl 208 dq44 i/o sstl 209 dq45 i/o sstl 214 dq46 i/o sstl 215 dq47 i/o sstl 98 dq48 i/o sstl 99 dq49 i/o sstl 107 dq50 i/o sstl 108 dq51 i/o sstl 217 dq52 i/o sstl 218 dq53 i/o sstl 226 dq54 i/o sstl 227 dq55 i/o sstl 110 dq56 i/o sstl 111 dq57 i/o sstl 116 dq58 i/o sstl 117 dq59 i/o sstl 229 dq60 i/o sstl 230 dq61 i/o sstl 235 dq62 i/o sstl 236 dq63 i/o sstl check bits 42 cb0 i/o sstl check bits 7:0 note: nc on non-ecc module 43 cb1 i/o sstl 48 cb2 i/o sstl 49 cb3 i/o sstl 161 cb4 i/o sstl 162 cb5 i/o sstl 167 cb6 i/o sstl 168 cb7 i/o sstl ball no. name pin type buffer type function
internet data sheet rev. 1.0, 2006-10 9 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module data strobe bus 7 dqs0 i/o sstl data strobes 17:0 6 dqs0 i/o sstl 16 dqs1 i/o sstl 15 dqs1 i/o sstl 28 dqs2 i/o sstl 27 dqs2 i/o sstl 37 dqs3 i/o sstl 36 dqs3 i/o sstl 84 dqs4 i/o sstl 83 dqs4 i/o sstl 93 dqs5 i/o sstl 92 dqs5 i/o sstl 105 dqs6 i/o sstl 104 dqs6 i/o sstl 114 dqs7 i/o sstl 113 dqs7 i/o sstl 46 dqs8 i/o sstl 45 dqs8 i/o sstl 125 dqs9 i/o sstl 126 dqs9 i/o sstl 134 dqs10 i/o sstl 135 dqs10 i/o sstl 146 dqs11 i/o sstl 147 dqs11 i/o sstl 155 dqs12 i/o sstl 156 dqs12 i/o sstl 202 dqs13 i/o sstl 203 dqs13 i/o sstl 211 dqs14 i/o sstl 212 dqs14 i/o sstl 223 dqs15 i/o sstl 224 dqs15 i/o sstl 232 dqs16 i/o sstl 233 dqs16 i/o sstl 164 dqs17 i/o sstl 165 dqs17 i/o sstl ball no. name pin type buffer type function
internet data sheet rev. 1.0, 2006-10 10 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module data mask 125 dm0 i sstl data masks 8:0 note: 8 based module 134 dm1 i sstl 146 dm2 i sstl 155 dm3 i sstl 202 dm4 i sstl 211 dm5 i sstl 223 dm6 i sstl 232 dm7 i sstl 164 dm8 i sstl eeprom 120 scl i cmos serial bus clock 119 sda i/o od serial bus data 239 sa0 i cmos serial address select bus 2:0 240 sa1 i cmos 101 sa2 i cmos parity 55 err_out ocmos parity bits par_in i cmos power supplies 1 v ref ai ? i/o reference voltage 238 v ddspd pwr ? eeprom power supply 51, 56, 62, 72, 75, 78, 170, 175,, 181, 191, 194 v ddq pwr ? i/o driver power supply 53, 59, 64, 67, 69, 172, 178, 184,, 187, 189, 197 v dd pwr ? power supply 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 v ss gnd ? ground plane ball no. name pin type buffer type function
internet data sheet rev. 1.0, 2006-10 11 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module table 6 abbreviations for buffer type table 7 abbreviations for ball type other balls 19, 55, 68, 102, 137, 138, 173, 220, 221 nc nc ? not connected 195 odt0 i sstl on-die termination control 1:0 note: 2-ranks module 77 odt1 i sstl nc nc ? note: 1-rank modules abbreviation description sstl serial stub terminated logic (sstl_18) cmos cmos levels od open drain. the corresponding ball has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. abbreviation description i standard input-only ball. digital levels. o output. digital levels. i/o i/o is a bidirectio nal input/output signal. ai input. analog levels. pwr power gnd ground nu not usable nc not connected ball no. name pin type buffer type function
internet data sheet rev. 1.0, 2006-10 12 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module figure 1 ball configuration fo r rdimm (240 balls) 0337 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 95() '4 9 66 '46 '4 9 66 '4 '46 9 66 1& 9 66 '4 '46 9 66 '4 '4 9 66 '46 5(6(7 9 66 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 &% 9 66 '46 &% 9 66 &.( 1&%$ 9 ''4 $ $ 9 ''4 9 '' 9 66 1& $$3 9 ''4 &$6 1&6 9 ''4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 '4 9 66 1& '46 9 66 '4 '4 9 66 '46 '4 9 66 6&/ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 &% '46 9 66 &% 9 ''4 9 '' 1& $ 9 '' $ $ 9 66 9 '' 9 '' %$ :( 9 ''4 1&2'7 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 '4 6$ 9 66 '46 '4 9 66 '4 '46 9 66 '4 6'$ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 '4 '0'46 9 66 '4 '4 9 66 1&'46 1& 9 66 '4 9 66 1&'46 '4 9 66 '4 '0'46 9 66 1& '4 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 '4 '0'46 9 66 '4 '4 9 66 1&'46 '4 9 66 &% '0'46 9 66 &% 9 ''4 9 '' 1&$ $ 9 '' $ $ 9 '' &. $ %$ 5$6 9 ''4 1&$ 9 66 '4 '0'46 9 66 '4 '4 9 66 1&'46 '4 9 66 '4 1& 9 66 1&'46 '4 9 66 '4 '0'46 9 66 '4 9''63' 6$ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '4 9 66 1&'46 '4 9 66 '4 '0'46 9 66 '4 &% 9 66 1&'46 &% 9 66 1&&.( 1&$ 9 ''4 $ $ 9 ''4 $ &. 9 '' 9 '' 9 ''4 6 2'7 9 '' '4 9 66 1&'46 '4 9 66 '4 '0'46 9 66 '4 '4 9 66 1& '0'46 9 66 '4 '4 9 66 1&'46 '4 9 66 6$ )52176,'( %$&.6,'(
internet data sheet rev. 1.0, 2006-10 13 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 3 electrical characteristics this chapter lists the el ectrical characteristics. 3.1 absolute maximum ratings caution is needed not to exceed absolute maximum ratings of the dram device listed in table 8 at any time. table 8 absolute maximum ratings attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. table 9 dram component operating temperature range symbol parameter rating unit note min. max. v dd voltage on v dd pin relative to v ss ?1.0 +2.3 v 1) 1) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 +2.3 v 1)2) v ddl voltage on v ddl pin relative to v ss ?0.5 +2.3 v 1)2) v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v 1) t stg storage temperature ?55 +100 c 1)2) 2) storage temperature is the case surface temperature on the center/top side of the dram. symbol parameter rating unit note min. max. t oper operating temperature 0 95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dram specification will be supported. during operation, the dr am case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 c the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c tcase tem perature range, the high temperature self refresh has to be enable d by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50%
internet data sheet rev. 1.0, 2006-10 14 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 3.2 dc operating conditions this chapter contains the dc operating conditions tables. table 10 operating conditions table 11 supply voltage levels an d dc operating conditions parameter symbol values unit note min. max. operating temperature (ambient) t opr 0+65 c dram case temperature t case 0+95 c 1)2)3)4) 1) dram component case temperature is the surface temperature in the center on the top side of any of the drams. 2) within the dram component case temperature range all dram specificat ions will be supported 3) above 85 c dram case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c t case temperature range, the high temperature self refresh has to be enabled by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50%. storage temperature t stg ? 50 +100 c barometric pressure (operating & storage) pbar +69 +105 kpa 5) 5) up to 3000 m. operating humidity (relative) h opr 10 90 % parameter symbol values unit note min. typ. max. device supply voltage v dd 1.7 1.8 1.9 v output supply voltage v ddq 1.7 1.8 1.9 v 1) 1) under all conditions, v ddq must be less than or equal to v dd input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc). v ref is also expected to track noise in v ddq . spd supply voltage v ddspd 1.7 ? 3.6 v dc input logic high v ih(dc) v ref + 0.125 ? v ddq +0.3 v dc input logic low v il (dc ) ? 0.30 ? v ref ? 0.125 v in / output leakage current i l ? 5 ? 5 a 3) 3) input voltage for any connector pin under test of 0 v v in v ddq + 0.3 v; all other pins at 0 v. current is per pin
internet data sheet rev. 1.0, 2006-10 15 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 3.3 timing characteristics this chapter describes the timing characteristics. 3.3.1 speed grade definitions all speed grades faster than ddr2-400b comp ly with ddr2-400b timing specifications( t ck = 5ns with t ras = 40ns). speed grade definitions: table 12 for ddr2?533c and table 13 for ddr2?400b table 12 speed grade definition speed bins for ddr2?533c table 13 speed grade defi nition speed bi ns for ddr2-400b speed grade ddr2?533c unit note qag sort name ?3.7 cas-rcd-rp latencies 4?4?4 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 3.75 8 ns 1)2)3)4) row active time t ras 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4) speed grade ddr2?400b unit note qag sort name ?5 cas-rcd-rp latencies 3?3?3 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) @ cl = 4 t ck 58 ns 1)2)3)4) @ cl = 5 t ck 58 ns 1)2)3)4) row active time t ras 40 70000 ns 1)2)3)4)5)
internet data sheet rev. 1.0, 2006-10 16 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 3.3.2 component ac timing parameters timing parameters: table 14 for ddr2?533c and table 15 for ddr2?400b table 14 dram component timing parameter by speed grade - ddr2?533 row cycle time t rc 55 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) . 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . parameter symbol ddr2?533 unit note 1)2)3)4)5) 6)7) min. max. dq output access time from ck / ck t ac ?500 +500 ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 8)18) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns 9) dq and dm input hold time (differential data strobe) t dh (base) 225 ?? ps 10) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps 11) dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ?450 + 450 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ps 11) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck speed grade ddr2?400b unit note qag sort name ?5 cas-rcd-rp latencies 3?3?3 t ck parameter symbol min. max. ?
internet data sheet rev. 1.0, 2006-10 17 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module dq and dm input setup time (differential data strobe) t ds (base) 100 ? ps 11) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps 11) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck four activate window period t faw 37.5 ? ns 50 ? ns 13) clock half period t hp min. ( t cl, t ch )? 12) data-out high-impedance time from ck / ck t hz ? t ac.max ps 13) address and control input hold time t ih (base) 375 ? ps 11) address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 250 ? ps 11) dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps 14) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 14) mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns data output hold time from dqs t qh t hp ? t qhs ?? data hold skew factor t qhs ? 400 ps average periodic refresh interval t refi ?7.8 s 14)15) ?3.9 s 16)18) auto-refresh to active/auto-refresh command period t rfc 127.5 ? ns 17) precharge-all (4 banks) command period t rp t rp +1 t ck ?ns precharge-all (8 banks) command period t rp 15 + 1 t ck ?ns read preamble t rpre 0.9 1.1 t ck 14) read postamble t rpst 0.40 0.60 t ck 14) active bank a to active bank b command period t rrd 7.5 ? ns 14)18) 10 ? ns 16)20) internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 x t ck ? t ck write postamble t wpst 0.40 0.60 t ck 19) write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck ? t ck 20) internal write to read command delay t wtr 7.5 ? ns 21) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 22) parameter symbol ddr2?533 unit note 1)2)3)4)5) 6)7) min. max.
internet data sheet rev. 1.0, 2006-10 18 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck 22) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 5)6)7)8) 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 9) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) for timing definition, refer to the component data sheet. 11) consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of t he output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 12) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the act ual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 13) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 14) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 15) 0 c t case 85 c 16) 85 c < t case 95 c 17) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 18) the t rrd timing parameter depends on the page size of the dram organization. see table 2 ?ordering information for rohs compliant products? on page 4 . 19) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 21) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 22) user can choose two different active pow er-down modes for additional power saving vi a mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. parameter symbol ddr2?533 unit note 1)2)3)4)5) 6)7) min. max.
internet data sheet rev. 1.0, 2006-10 19 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module table 15 dram component timing parameter by speed grade - ddr2-400 parameter symbol ddr2?400 unit note 1)2)3)4)5) 6)7) min. max. dq output access time from ck / ck t ac ?600 +600 ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 8)22) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns 9) dq and dm input hold time (differential data strobe) t dh (base) 275 ?? ps 10) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps 11) dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ?500 + 500 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 350 ps 11) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setup time (differential data strobe) t ds (base) 150 ? ps 11) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps 11) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck four activate window period t faw 37.5 ? ns 50 ? ns 13) clock half period t hp min. ( t cl, t ch ) 12) data-out high-impedance time from ck / ck t hz ? t ac.max ps 13) address and control input hold time t ih (base) 475 ? ps 11) address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 350 ? ps 11) dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps 14) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 14) mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns data output hold time from dqs t qh t hp ? t qhs ??
internet data sheet rev. 1.0, 2006-10 20 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module data hold skew factor t qhs ? 450 ps average periodic refresh interval t refi ?7.8 s 14)15) ?3.9 s 16)18) auto-refresh to active/auto-refresh command period 127.5 ? ns 17) precharge-all (4 banks) command period t rp t rp +1 t ck ?ns precharge-all (8 banks) command period t rp 15 + 1 t ck ?ns read preamble t rpre 0.9 1.1 t ck 14) read postamble t rpst 0.40 0.60 t ck 14) active bank a to active bank b command period t rrd 7.5 ? ns 14)18) 10 ? ns 16)20) internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 x t ck ? t ck write postamble t wpst 0.40 0.60 t ck 19) write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck ? t ck 20) internal write to read command delay t wtr 10 ? ns 21) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 22) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck 22) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 5)6)7)8) 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 9) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) for timing definition, refer to the component data sheet. 11) consists of data pin skew and output pattern effects, and p-channel to n-channel variation of t he output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 12) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). parameter symbol ddr2?400 unit note 1)2)3)4)5) 6)7) min. max.
internet data sheet rev. 1.0, 2006-10 21 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 3.3.3 odt ac electrical characteristics table 16 odt ac character. and operating co nditions for ddr2 -533 & ddr2-400 13) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 14) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 15) 0 c t case 85 c 16) 85 c < t case 95 c 17) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 18) the t rrd timing parameter depends on the page size of the dram organization. see table 2 ?ordering information for rohs compliant products? on page 4 . 19) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 21) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 22) user can choose two different active power-down modes for addi tional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min is when the device leaves high impedance and odt re sistance begins to turn on. odt turn on time max is w hen the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2-400/533, t aond is 10 ns (= 2 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-400/533, t aofd is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck
internet data sheet rev. 1.0, 2006-10 22 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 3.4 i dd specifications and conditions list of tables defining i dd specifications and conditions. ? table 17 ?idd measurement conditions? on page 22 ? table 18 ?definitions for idd? on page 23 ? table 19 ?idd specification for hys72t256000er?[3.7/5]?b? on page 24 table 17 i dd measurement conditions parameter symbol note 1)2)3)4)5) operating current 0 one bank active - precharge; t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , t rcd = t rcd.min , al = 0, cl = cl min ; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 6) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are switching, databus inputs are switching. i dd2n precharge power-down current other control and address inputs are st able, data bus inputs are floating. i dd2p precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are stable, data bus inputs are floating. i dd2q active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max , t rp = t rp.min ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n active power-down current all banks open; t ck = t ck.min , cke is low; other control and addres s inputs are stable, data bus inputs are floating. mrs a12 bit is se t to low (fast power-down exit); i dd3p(0) active power-down current all banks open; t ck = t ck.min , cke is low; other control and addre ss inputs are stable, data bus inputs are floating. mrs a12 bit is set to high (slow power-down exit); i dd3p(1) operating current - burst read all banks open; continuous burst re ads; bl = 4; al = 0, cl = cl min ; t ck = t ckmin ; t ras = t rasmax ; t rp = t rpmin ; cke is high, cs is high between valid co mmands; address inputs are switching; data bus inputs are switching; i out = 0ma. i dd4r 6) operating current - burst write all banks open; continuous burst wr ites; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max. , t rp = t rp.max ; cke is high, cs is high between valid commands. address inputs are switching; data bus in puts are switching; i dd4w burst refresh current t ck = t ck.min ., refresh command every t rfc = t rfc.min interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b
internet data sheet rev. 1.0, 2006-10 23 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module table 18 definitions for i dd distributed refresh current t ck = t ck.min. , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5d self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and addr ess inputs are floating, data bus inputs are floating. i dd6 current values are guaranteed up to t case of 85 c max. i dd6 all bank interleave read current all banks are being interleaved at minimum t rc without violating t rrd using a burst length of 4. control and address bus inputs are stable during deselects. i out = 0 ma. i dd7 6) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) i dd specifications are tested after t he device is properly initialized and i dd parameter are specified with odt disabled. 3) definitions for i dd see table 18 4) for two rank modules: for all active current meas urements the other rank is in precharge power-down mode i dd2p 5) for details and notes see the relevant qimonda component data sheet 6) i dd1 , i dd4r and i dd7 current measurements are defined with the outputs disabled ( i out = 0 ma). to achieve this on module level the output buffers can be disabled using an emrs(1) (extended m ode register command) by setting a12 bit to high. parameter description low v in v il(ac).max , high is defined as v in v ih(ac).min stable inputs are stable at a high or low level floating inputs are v ref = v ddq /2 switching inputs are changing between hi gh and low every other clock (once per 2 cycles) for address and control signals, and inputs changing between high and low every other data transfer (once per cycle) for dq signals not including mask or strobes parameter symbol note 1)2)3)4)5)
internet data sheet rev. 1.0, 2006-10 24 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module table 19 i dd specification for hys72t256000er?[3.7/5]?b product type hys72t256000er?3.7?b hys72t256000er?5?b units note 1) 1) module i dd is calculated on the basis of component i dd and includes currents of registers and pll. odt disabled. i dd1, i dd4r, and i dd7, are defined with the outputs disabled. organization 2 gb 2 gb 72 72 1 ranks 1 ranks ?3.7 ?5 i dd0 2300 2120 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 2390 2210 ma 2) i dd2p 720 620 ma 3) 3) both ranks are in the same i dd current mode i dd2n 1490 1310 ma 3) i dd2q 1400 1220 ma 3) i dd3p_0 (fast) 1180 1040 ma 3) i dd3p_1 (slow) 770 680 ma 3)4) 4) fast: mrs(12)=0 i dd3n 1580 1400 ma 3)5) 5) slow: mrs(12)=1 i dd4r 3200 2840 ma 2) i dd4w 3200 2840 ma 2) i dd5b 4100 3830 ma 2) i dd5d 730 640 ma 3)6) 6) i dd5d and i dd6 values are for 0 c t case 85 c i dd6 180 180 ma 3)6) i dd7 4550 4280 ma 2)
internet data sheet rev. 1.0, 2006-10 25 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 4 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 20 ?spd codes for pc2?4200?444 & pc2?3200?333? on page 25 table 20 spd codes for pc2?4200?444 & pc2?3200?333 product type hys72t256000er?3.7?b hys72t256000er?5?b organization 2 gbyte 2 gbyte 72 72 1 rank ( 4) 1 rank ( 4) label code pc2?4200r?444 pc2?3200r?333 jedec spd revision rev. 1.2 rev. 1.2 byte# description hex hex 0 programmed spd bytes in eeprom 80 80 1 total number of bytes in eeprom 08 08 2 memory type (ddr2) 08 08 3 number of row addresses 0e 0e 4 number of column addresses 0b 0b 5 dimm rank and stacking information 60 60 6 data width 48 48 7 not used 00 00 8 interface voltage level 05 05 9 t ck @ cl max (byte 18) [ns] 3d 50 10 t ac sdram @ cl max (byte 18) [ns] 50 60 11 error correction supp ort (non-ecc, ecc) 02 02 12 refresh rate and type 82 82 13 primary sdram width 04 04 14 error checking sdram width 04 04 15 not used 00 00 16 burst length supported 0c 0c 17 number of banks on sdram device 08 08 18 supported cas latencies 38 38 19 dimm mechanical characteristics 01 01 20 dimm type information 01 01 21 dimm attributes 05 05
internet data sheet rev. 1.0, 2006-10 26 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 22 component attributes 07 07 23 t ck @ cl max -1 (byte 18) [ns] 3d 50 24 t ac sdram @ cl max -1 [ns] 50 60 25 t ck @ cl max -2 (byte 18) [ns] 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 27 t rp.min [ns] 3c 3c 28 t rrd.min [ns] 1e 1e 29 t rcd.min [ns] 3c 3c 30 t ras.min [ns] 2d 28 31 module density per rank 02 02 32 t as.min and t cs.min [ns] 25 35 33 t ah.min and t ch.min [ns] 37 47 34 t ds.min [ns] 10 15 35 t dh.min [ns] 22 27 36 t wr.min [ns] 3c 3c 37 t wtr.min [ns] 1e 28 38 t rtp.min [ns] 1e 1e 39 analysis characteristics 00 00 40 t rc and t rfc extension 06 06 41 t rc.min [ns] 3c 37 42 t rfc.min [ns] 7f 7f 43 t ck.max [ns] 80 80 44 t dqsq.max [ns] 1e 23 45 t qhs.max [ns] 28 2d 46 pll relock time 0f 0f 47 t case.max delta / ? t 4r4w delta 52 51 48 psi(t-a) dram 60 60 49 ? t 0 (dt0) 37 33 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 20 1d 51 ? t 2p (dt2p) 2b 2b 52 ? t 3n (dt3n) 20 1c 53 ? t 3p.fast (dt3p fast) 35 2c 54 ? t 3p.slow (dt3p slow) 21 21 product type hys72t256000er?3.7?b hys72t256000er?5?b organization 2 gbyte 2 gbyte 72 72 1 rank ( 4) 1 rank ( 4) label code pc2?4200r?444 pc2?3200r?333 jedec spd revision rev. 1.2 rev. 1.2 byte# description hex hex
internet data sheet rev. 1.0, 2006-10 27 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 36 2c 56 ? t 5b (dt5b) 22 21 57 ? t 7 (dt7) 25 24 58 psi(ca) pll c4 c4 59 psi(ca) reg 8c 8c 60 ? t pll (dtpll) 61 59 61 ? t reg (dtreg) / toggle rate 78 5c 62 spd revision 12 12 63 checksum of bytes 0-62 c9 fe 64 manufacturer?s jedec id code (1) 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 69 manufacturer?s jedec id code (6) 51 51 70 manufacturer?s jedec id code (7) 00 00 71 manufacturer?s jedec id code (8) 00 00 72 module manufacturer location xx xx 73 product type, char 1 37 37 74 product type, char 2 32 32 75 product type, char 3 54 54 76 product type, char 4 32 32 77 product type, char 5 35 35 78 product type, char 6 36 36 79 product type, char 7 30 30 80 product type, char 8 30 30 81 product type, char 9 30 30 82 product type, char 10 45 45 83 product type, char 11 52 52 84 product type, char 12 33 35 85 product type, char 13 2e 42 86 product type, char 14 37 20 87 product type, char 15 42 20 product type hys72t256000er?3.7?b hys72t256000er?5?b organization 2 gbyte 2 gbyte 72 72 1 rank ( 4) 1 rank ( 4) label code pc2?4200r?444 pc2?3200r?333 jedec spd revision rev. 1.2 rev. 1.2 byte# description hex hex
internet data sheet rev. 1.0, 2006-10 28 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 88 product type, char 16 20 20 89 product type, char 17 20 20 90 product type, char 18 20 20 91 module revision code 3x 3x 92 test program revision code xx xx 93 module manufacturing date year xx xx 94 module manufacturing date week xx xx 95 - 98 module serial number xx xx 99 - 127 not used 00 00 128 - 255 blank for customer use ff ff product type hys72t256000er?3.7?b hys72t256000er?5?b organization 2 gbyte 2 gbyte 72 72 1 rank ( 4) 1 rank ( 4) label code pc2?4200r?444 pc2?3200r?333 jedec spd revision rev. 1.2 rev. 1.2 byte# description hex hex
internet data sheet rev. 1.0, 2006-10 29 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 5 package outlines this chapter contains the package outlines of the products. figure 2 package outline raw card h lg-dim-240-13 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * /' % & $ & ? 0 $; % ? % x u u p d [ d o o r z h g ? $ % & ' h w d l o r i f r q w d f w v ? $ ? [
internet data sheet rev. 1.0, 2006-10 30 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 6 product type nomenclature qimondas nomenclature uses simple codi ng combined with some propriatory coding. table 21 provides examples for module and component product type number as well as the field number. the detailed field description together with possible values and coding explanation is listed for modules in table 22 and for components in table 23 . table 21 nomenclature fields and examples table 22 ddr2 dimm nomenclature example for field number 1234567891011 micro-dimm hys 64 t 64/128 0 2 0 k m ?5 ?a ddr2 dram hyb 18 t 512/1g 16 0 a c ?5 field description values coding 1 qimonda module prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3 dram technology t ddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 512 4 gbyte 5 raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type d so- d imm m m icro-dimm r r egistered u u nbuffered f f ully buffered
internet data sheet rev. 1.0, 2006-10 31 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module table 23 ddr2 dram nomenclature 10 speed grade ?2.5f pc2?6400 5?5?5 ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the o verall module memory density in mbytes as listed in column ?coding?. field description values coding 1 qimonda component prefix hyb constant 2 interface voltage [v] 18 sstl_18 3 dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free stat us c fbga, lead-containing f fbga, lead-free 10 speed grade ?25f ddr2-800 5-5-5 ?2.5 ddr2-800 6-6-6 ?3 ddr2-667 4-4-4 ?3s ddr2-667 5-5-5 ?3.7 ddr2-533 4-4-4 ?5 ddr2-400 3-3-3 field description values coding
internet data sheet rev. 1.0, 2006-10 32 10202006-ehwj-ot02 hys72t256000er-[3.7/5]-b registerd ddr2 sdram module 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 chip configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 chip configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.2 component ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 product type nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table of contents
edition 2006-10 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2006. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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